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ds201 (v2.1) june 24, 2002 www.xilinx.com 1 product specification 1-800-255-7778 ? 2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to change with out notice. notice of disclaimer: xilinx is providing this design, code, or information "as is." by providing the design, code, or informat ion as one possible implementation of this feature, application, or standard, xilinx makes no representation that this implementation is free from any claims of infringement. you are responsible for obtaining any rights you may require for your implementation. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the impleme ntation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability o r fitness for a particular purpose. features ? single-speed full-duplex 10-gigabits-per-second ethernet media access controller designed to draft d4.1 of ieee p802.3ae specification choice of xgmii or xaui interface to phy layer uses virtex ? -ii ddr i/o primitives for the optional xgmii interface uses virtex-ii pro ? multi gigabit transceivers for the optional xaui interface cut-through operation with minimum buffering for maximum flexibility in 64-bit client bus interfacing configured and monitored through an independent microprocessor-neutral interface uses virtex-ii/virtex-ii pro digital clock management to implement xgmii and xaui interface timing powerful statistics gathering to internal counters. statistics vectors are also output to the user. configurable flow control through mac control pause frames; symmetrically or asymmetrically enabled new-style clause 45 mdio interface to managed objects in phy layers supports lan/wan (oc-192c data rate) functionality through open loop rate control configurable support of vlan frames to specification ieee 802.3-2000 configurable support of ? jumbo frames ? of any length configurable interframe gap length adjustment remote fault/local fault signalling at the reconciliation sublayer available under terms of the signonce ip license 0 10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 00 product specification logicore? facts core specifics supported families virtex-ii, virtex-ii pro speed grades -5 speed grade on virtex-ii (xgmii version only) -7 speed grade on virtex-ii pro performance 156.25 mhz internal clock; 156.25mhz ddr on xgmii interface; 3.125gbps per lane on xaui interface size 3000-4400 slices global clock buffers 3 special features digital clock management integrated into core provided with core documentation product specification design file formats edif netlist constraints file .ucf design tools requirements xilinx core tools v4.2i sp2 support support provided by xilinx figure 1: typical 10-gigabit ethernet architecture tcp ip fifo i/f mac pcs wis pma pmd xip2092
10-gigabit ethernet mac with xgmii or xaui v2.1 2 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r overview the 10-gigabit ethernet mac is part of the 10-gigabit ether- net architecture displayed in figure 1 . the part of this archi- tecture from the mac to the right is defined in draft d4.1 specification of the ieee p802.3ae task force , currently under development and due to be ratified in may 2002. a block diagram of the mac core can be seen in figure 2 . this shows the major functional blocks of the mac, which are: the client interface the transmit engine the flow control block the receive engine the reconciliation sublayer (rs) the configuration block the statistics block the mii management interface (miim) the optional xgmii interface the optional xaui interface the client interface has fully independent 64-bit interfaces for both transmit and receive to support full duplex opera- tion; control lines are associated with each port to delineate data lanes within the 64 bits. the configuration block and the statistics block are both accessed through the management interface, a 32-bit pro- cessor-neutral data pathway that is independent of the ethernet data pathway. the miim port is also accessed through this interface. the rs either converts the internal data representation of the mac core to the 32-bit ddr data that the xgmii speci- fication requires, or passes it to the xaui block. it also con- tains logic to handle local fault and remote fault signalling across the link. the optional xaui interface is designed to clause 47 of the ieee p802.3ae d4.1 draft. it uses the multi gigabit trans- ceivers (mgts) of the virtex-ii pro family. it converts the mac data into 4 lanes of 3.125gbps data for transmission over current mode differential lines, and also receives four lanes of data at the same rate and passes it to the mac. figure 2: functional block diagram of the 10-gigabit ethernet mac flow control transmit engine receive engine reconciliation sublayer optional xgmii interface optional xaui interface host interface configuration statistics miim client interface management interface xip2093
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 3 product specification 1-800-255-7778 r interface description client interface signals figure 3 shows the pinout for a mac core with the optional xgmii interface. figure 3: core pinout with xgmii interface gtx_clk xgmii_rx_clk mdc mdio_in mdio_out mdio_tri xgmii_rxd[31:0] xgmii_rxc[3:0] xgmii_txd[31:0] xgmii_txc[31:0] xgmii_tx_clk tx_underrun pause_req pause_val[15:0] rx_clk host_clk host_opcode[1:0] host_addr[9:0] host_wr_data[31:0] host_rd_data[31:0] host_miim_sel host_req host_miim_rdy reset rx_data[63:0] rx_data_valid[7:0] rx_good_frame rx_bad_frame tx_clk tx_data[63:0] tx_data_valid[7:0] tx_start tx_ack tx_clk domain rx_clk domain host_clk domain tx_statistics_vector[21:0] tx_statistics_valid tx_ifg_delay[7:0] rx_statistics_vector[24:0] rx_statistics_valid xip2094
10-gigabit ethernet mac with xgmii or xaui v2.1 4 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r figure 4 shows the pinout of a mac core with the optional xaui interface. table 1 describes the client-side transmitter interface signals of the mac core. these signals are used to transmit data from the client to the mac core. figure 4: core pinout with xaui interface table 1: transmit client interface signal pins signal direction description tx_clk output clock for transmit client interface. 156.25 mhz nominal. tx_data[63:0] input frame data to be transmitted is supplied on this port. tx_data_valid[7:0] input control signals for tx_data port. each asserted signal on tx_data_valid signifies which bytes of tx_data are valid; i.e., if tx_data_valid[0] is 1, the signal tx_data[7:0] is valid. refclk mdc mdio_in mdio_out mdio_tri xaui_tx_l0 xaui_rx_l0 tx_underrun pause_req pause_val[15:0] rx_clk host_clk host_opcode[1:0] host_addr[9:0] host_wr_data[31:0] host_rd_data[31:0] host_miim_sel host_req host_miim_rdy reset rx_data[63:0] rx_data_valid[7:0] rx_good_frame rx_bad_frame xaui_tx_l1 xaui_rx_l1 xaui_tx_l2 xaui_rx_l2 xaui_tx_l3 xaui_rx_l3 signal_detect[3:0] xaui_type_sel xaui_prtad[4:0] tx_clk tx_data[63:0] tx_data_valid[7:0] tx_start tx_ack tx_clk/rx_clk domain host_clk domain tx_statistics_vector[21:0] tx_statistics_valid tx_ifg_delay[7:0] rx_statistics_vector[24:0] rx_statistics_valid xip2095
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 5 product specification 1-800-255-7778 r table 2 describes the signals used by the host to request a flow control action from the transmit engine. flow control frames received by the mac across the xgmii or xaui are automatically handled (if the mac is configured to do so). table 3 describes the client-side receive signals. these signals are used by the mac core to transfer data to the client. tx_start input handshaking signal. asserted by the client to make data available for transmission. see the timing diagrams in section "transmitter" on page 8 . tx_ack output asserted when the current data on tx_data has been accepted. see timing diagrams in section "transmitter" on page 8 . tx_underrun input asserted by client to force mac to corrupt the current frame. tx_ifg_delay[7:0] input enables the user to select a minimum interframe gap size. see timing diagrams in section "transmitter" on page 8 . tx_statistics_vector[21:0] output this gives information on the last frame transmitted. the contents of the vector are described in section "xgmii interface" on page 29 . tx_statistics_valid output this is asserted when the data on the tx_statistics_vector is valid. notes: 1. all the above signals are synchronous to tx_clk and active high. table 2: flow control interface signal pinout signal direction description pause_req input pause request; sends a pause frame down the link. pause_val[15:0] input pause value; this value is inserted into the parameter field of the transmitted pause frame. notes: 1. these signals are synchronous to tx_clk and are active high. table 3: receive client interface signal pins signal direction description rx_clk output clock for receiving client interface. 156.25 mhz nominal. rx_data[63:0] output frame data received is supplied on this port. rx_data_valid[7:0] output control signals for the rx_data port. each asserted signal on rx_data_valid signifies which bytes of rx_data are valid. e.g., if rx_data_valid[0] is 1, the signal rx_data[7:0] is valid. rx_good_frame output asserted at end of reception of compliant frame. see "receiver" on page 16. rx_bad_frame output asserted at end of noncompliant frame. see "receiver" on page 16. rx_statistics_vector[24:0] output information on the last frame received. the contents of the vector are described in section "xgmii interface" on page 29 . rx_statistics_valid output this is driven high when the rx_statistics_vector is valid. notes: 1. all signals above are synchronous to rx_clk and active high. table 1: transmit client interface signal pins (continued) signal direction description
10-gigabit ethernet mac with xgmii or xaui v2.1 6 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r table 4 describes the signals used by the host system to access the management features of the mac core, including configuration, status, statistics and miim access. table 5 describes the xgmii signals of the mac core. these signals are optional. these are typically attached to an off-chip phy module. table 4: management interface signal pinout signal direction description host_clk input clock for management interface. see "management interface" on page 22 for the frequency range of this signal. host_opcode[1:0] input defines operation to be performed over management interface. host_addr[9:0] input address of register to be accessed. host_wr_data[31:0] input data to write to register. host_rd_data[31:0] output data read from register. host_miim_sel input when asserted, the miim interface is accessed. when disasserted, the mac internal registers are accessed. host_req input used to signal a transaction on the miim interface and to read from the statistic registers. see "management interface" on page 22. host_miim_rdy output when high, the miim interface has completed any pending transaction and is ready for a new transaction. reset input asynchronous reset for entire core. this must be asserted for a minimum of 500 ns for a valid reset to occur. the clocks must be running for the core to come out of the reset state. notes: 1. all signals above except reset are synchronous to host_clk and are active high. table 5: xgmii interface signal pinout signal direction description gtx_clk input clock signal at 156.25mhz. other transmit clocks are derived from this using dcm. tolerance must be within that specified in the ieee p802.3 ethernet specification. xgmii_tx_clk output clock to phy; source centred with respect to transmit data. xgmii_txd[31:0] output transmit data to phy; double data rate (ddr) signalling. xgmii_txc[3:0] output control lines to phy. xgmii_rx_clk input recovered clock from received data stream by phy. xgmii_rxd[31:0] input received data from phy; ddr signalling. xgmii_rxc[3:0] input control lines from phy.
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 7 product specification 1-800-255-7778 r table 6 describes the xaui signals of the mac core. these signals are optional and are typically attached to a backplane or phy module. table 7 describes the miim interface signals of the mac core. these signals are typically connected to the miim port of an off-chip phy. table 6: xaui interface signal pinout signal direction description refclk input clock signal at 156.25 mhz. all other core clocks are derived from this using a dcm. must conform to mgt jitter and stability specifications. see virtex-ii pro databook. xaui_tx_l0_ output transmit differential pair, xaui lane 0 xaui_tx_l1_ output transmit differential pair, xaui lane 1 xaui_tx_l2_ output transmit differential pair, xaui lane 2 xaui_tx_l3_ output transmit differential pair, xaui lane 3 xaui_rx_l0_ input receive differential pair, xaui lane 0 xaui_rx_l1_ input receive differential pair, xaui lane 1 xaui_rx_l2_ input receive differential pair, xaui lane 2 xaui_rx_l3_ input receive differential pair, xaui lane 3 signal_detect[3:0] input signals from an 10g base-lx4 optical module, w hen the xaui block is used as a 10gbase-x pcs. when the xaui block is used as an xgxs, these signals have no effect. xaui_type_sel i nput selects which type of xaui block is implemented. when xaui_type_sel = 0, the block behaves as a 10g base-x pcs. when xaui_type_sel = 1, the block behaves as a dte xgxs. xaui_prtad[4:0] input sets the port address at which the xaui block should appear on the miim bus. table 7: miim interface signal pinout signal direction description mdc output management clock; derived from host_clk on basis of supplied configuration data. see "management interface" on page 22. mdio_in input serial mdio data signal from phy. mdio_out output serial mdio data signal to phy mdio_tri output tristate control for mdio signals; ? 0 ? signals that the value on mdio_out should be asserted onto the mdio bus.
10-gigabit ethernet mac with xgmii or xaui v2.1 8 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r functional description client interface the client interface is designed for maximum flexibility in matching to a client switching fabric or network processor interface. the data pathway is 64 bits wide in both the transmit and receive directions, with each pathway synchronous to the tx_clk and rx_clk respectively for completely indepen- dent full duplex operation. there are 8 control lines associ- ated with each interface to signal which byte lanes are active in each clocked transfer ( ta ble 8 ). for each of tx_data and rx_data, the port is logically divided into lane 0 to lane 7, with the corresponding bit of the control word signifying valid data on the tx_data, rx_data port. transmitter normal frame transmission ta ble 8 : tx_data, rx_data lanes lane tx_data, rx_data bits 07:0 1 15:8 2 23:16 3 31:24 4 39:32 5 47:40 6 55:48 7 63:56 figure 5: normal frame transmission across client interface tx_clk tx_data[7:0] tx_data[15:8] tx_data[23:16] tx_data[31:24] tx_data[39:32] tx_data[47:40] tx_data[55:48] tx_data[63:56] tx_data_valid[7:0] tx_start tx_ack tx_underrun da da da da da sa sa ff 00 00 ff ff sa sa sa sa l/t l/t d d d d d d d d d d ff 07 d d d d d d d d d d d da xip2096
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 9 product specification 1-800-255-7778 r the timing of a normal outbound frame transfer is shown in figure 5 . when the client wants to transmit a frame, it asserts the tx_start signal, and on the next clock places the first column of data and control onto the tx_data and tx_data_valid ports. when the mac core has read this first column of data, it will assert the tx_ack signal; on the next and subsequent clock edges, the client must provide the remainder of the data for the frame. the end of frame is signalled to the mac core by having tx_data_valid not equal to hexadecimal ? ff ? ; partially full columns of data are not permitted within a frame. as an example, in figure 5 , the value of tx_data_valid of hexa- decimal ? 07 ? signals to the mac core that only the lower three columns of data are valid on the transfer, and addition- ally that the end of frame has been reached. frame parameters (destination address, source address, length/type and optionally fcs) must be supplied on the data bus according to the timing diagram. the definitions of the abbreviations are described in ta ble 9 . in-band parameter encoding for maximum flexibility in switching applications, the ether- net frame parameters are encoded within the same data stream that the frame payload is transferred upon, rather than on separate ports. the destination address must be supplied with the first byte in lane 0 and so on. similarly, the first byte of the source address must be supplied in lane 6 of the first transfer. the length/type field is similarly encoded, with the first byte placed into lane 4. client-supplied fcs passing if the mac core is configured to have the fcs field passed by the client (see "configuration registers" on page 22 ), the transmission timing is as shown in figure 6 . in this case, it is the responsibility of the client to ensure that the frame meets the ethernet minimum frame length requirements; the mac core will not perform any padding of the payload. ta ble 9 : abbreviations used in timing diagrams abbreviation definition da destination address sa source address l/t length/type field fcs frame check sequence
10-gigabit ethernet mac with xgmii or xaui v2.1 10 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r padding when fewer than 46 bytes of data are supplied by the client to the mac core, the transmitter module will add padding up to the minimum frame length, unless the mac core is con- figured for client-passed fcs. in the latter case, the client must also supply the padding in order to maintain the mini- mum frame length. client underrun the timing of an aborted transfer can be seen in figure 7 . this may happen, for instance, if a fifo in the bus interface empties before a frame is completed. when the client asserts tx_underrun during a frame transmission, the mac core will insert error codes into the xgmii data stream in order to corrupt the current frame, then will fall back to idle transmission. it is the responsibility of the client to requeue the aborted frame for transmission. when an underrun occurs, tx_start may be asserted on the clock cycle after the tx_underrun assertion to start a new transmission. figure 6: frame transmission with client-supplied fcs tx_clk tx_data[7:0] tx_data[15:8] tx_data[23:16] tx_data[31:24] tx_data[39:32] tx_data[47:40] tx_data[55:48] tx_data[63:56] tx_data_valid[7:0] tx_start tx_ack tx_underrun da da da da da sa sa ff 00 00 ff ff sa sa sa sa l/t l/t d d d d d d d d d d ff 7f d d d d d d fcs fcs fcs fcs d d d d d da xip2097
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 11 product specification 1-800-255-7778 r back-to-back transfers two situations can occur during back-to-back transfers; in one, the mac core is ready to accept data; in the other, the mac must defer to comply with inter-packet gap require- ments, a user request to extend the interframe gap or flow control requests. figure 8 shows the case where the mac is immediately ready to accept the next frame of data. in the column after the last data is transferred for the first frame, the client asserts tx_start to signal that another frame is ready for transmission. the mac core then asserts tx_ack to allow the client to begin the burst of frame parameters and data that make up the frame. figure 7: frame transmission with underrun tx_clk tx_data[7:0] tx_data[15:8] tx_data[23:16] tx_data[31:24] tx_data[39:32] tx_data[47:40] tx_data[55:48] tx_data[63:56] tx_data_valid[7:0] tx_start tx_ack tx_underrun da da da da da sa sa ff 00 00 ff ff sa sa sa sa l/t l/t d d d d d d d d d d ff d d d d d d d d da xip2098
10-gigabit ethernet mac with xgmii or xaui v2.1 12 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r figure 9 shows a case where the mac is exerting back pressure on the client to delay the start of transmission. in this case, the client has asserted tx_start to signal that another frame is ready for transmission, but the mac core has delayed the assertion of tx_ack to allow the data burst to begin. once this burst has begun, it continues in the same manner as in the cases above. in both cases, as in the case for normal frame transmission, the client must pro- vide a whole frame of data in one burst; there is no mecha- nism to stop and start transfer within a single frame. figure 8: back to back frame transmission with no back pressure tx_clk tx_data[7:0] tx_data[15:8] tx_data[23:16] tx_data[31:24] tx_data[39:32] tx_data[47:40] tx_data[55:48] tx_data[63:56] tx_data_valid[7:0] tx_start tx_ack tx_underrun da da da da da sa sa ff ff ff sa sa sa sa l/t l/t d d d d d d d d d d ff 0f 00 d d d d d d d d d d d d da xip2099
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 13 product specification 1-800-255-7778 r interframe gap adjustment the user can elect to vary the length of the interframe gap. if this function is selected (via a configuration bit, see "con- figuration registers" on page 22 ), the mac will exert back pressure to delay the transmission of the next frame until the requested number of xgmii columns has elapsed. the number of xgmii columns is controlled by the value on the ifg_delay port. the minimum interframe gap of 3 xgmii columns is always maintained. figure 10 shows the mac operating in this mode. if the core has a xaui interface rather than a xaui one, the interframe gap will vary as if an xgmii interface existed. figure 9: back-to-back frame transmission with back pressure tx_clk tx_data[7:0] tx_data[15:8] tx_data[23:16] tx_data[31:24] tx_data[39:32] tx_data[47:40] tx_data[55:48] tx_data[63:56] tx_data_valid[7:0] tx_start tx_ack tx_underrun da da da da da sa sa ff ff ff sa sa sa sa l/t l/t d d d d d d d d d d ff 0f 00 d d d d d d d d d d d d da xip2100
10-gigabit ethernet mac with xgmii or xaui v2.1 14 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r vlan tagged frames transmission of a vlan tagged frame (if enabled) is shown in figure 11 . note that the handshaking signals across the interface do not change; however, the vlan type tag 81-00 must be supplied by the client to signify that the frame is vlan tagged. the client also supplies the two bytes of tag control information, v1 and v2, at the appropriate times in the data stream. more information on the contents of these two bytes can be found in ieee 802.3-2000. figure 10: interframe gap adjustment tx_clk tx_data[7:0] tx_data[15:8] tx_data[23:16] tx_data[31:24] tx_data[39:32] tx_data[47:40] tx_data[55:48] tx_data[63:56] tx_data_valid[7:0] tx_start tx_ack da da da da da sa sa ff 00 00 ff ff sa sa sa sa l/t l/t d d d d d d d d d d ff 07 d d d d d d d d d d d da tx_ifg_delay ifg_delay_val xip2101
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 15 product specification 1-800-255-7778 r transmitter statistics vector the statistics for the frame transmitted are contained within the tx_statistics_vector. the vector is synchronous to the transmitter clock, tx_clk and is driven following frame transmission. the bit field definition for the vector is defined in table 10 . all bit fields, with the exception of byte_valid, are valid only when the tx_statistics_valid is asserted. this is illustrated in figure 12 . byte_valid is significant on every tx_clk cycle. figure 11: transmission of a vlan tagged frame. tx_clk tx_data[7:0] tx_data[15:8] tx_data[23:16] tx_data[31:24] tx_data[39:32] tx_data[47:40] tx_data[55:48] tx_data[63:56] tx_data_valid[7:0] tx_start tx_ack tx_underrun da da da da da sa sa ff 00 00 ff ff sa sa sa sa 81 00 v1 v2 l/t l/t d d d d d d ff 07 d d d d d d d d d d d da xip2102 figure 12: transmitter statistics output timing. tx_clk tx_statistics_vector[21:0] tx_statistics_valid xip2103
10-gigabit ethernet mac with xgmii or xaui v2.1 16 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r receiver normal frame reception the timing of a normal inbound frame transfer is represented in figure 13 . the client must be prepared to accept data at any time; there is no buffering within the mac to allow for latency in the receive client. once frame reception begins, data is transferred on consecutive clock cycles to the receive client until the frame is complete. the mac asserts the rx_good_frame signal to signal successful frame reception to the client. table 10: tx_statistics_vector description tx stats vector bit name description 21 pause frame transmitted the previous frame was a pause frame that was initiated by the mac in response to a pause request from the client. 20 to 17 number of bytes the number of bytes transmitted on the last clock cycle. this can be between 0 and 8. this is valid on every clock cycle, it is not validated by tx_statistics_valid. 16 vlan frame high along with the valid signal when the previous frame was a vlan frame. 15 to 5 length count the length of the previously transmitted frame. this does not take into account the preamble or start bytes. the count will stick at 2047 for any jumbo frames larger than this value. 4 control frame indicates that the previous frame had the special control frame character in the length/type field. 3 underrun frame high if the previous frame contained an underrun error. 2 multicast frame high if the destination address in the previous frame contained a multicast address. 1 broadcast frame high if the destination address in the previous frame contained a broadcast address. 0 successful frame high if the previous frame was transmitted successfully.
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 17 product specification 1-800-255-7778 r frame parameters (destination address, source address, length/type and, optionally, fcs) are supplied on the data bus as shown on the timing diagram. the abbreviations are described in ta ble 9 . if the length/type field in the frame has the length interpretation, and this indicates that the inbound frame has been padded to meet the ethernet minimum frame size specification, this pad will not be passed to the client in the data payload. an exception to this occurs when fcs passing is enabled. see "client-supplied fcs passing" on page 19 . there is always at least one clock cycle with rx_data_valid = 0x00 between frames; i.e., there ? s no valid data for this clock edge. rx_good_frame, rx_bad_frame timing although the timing diagram in figure 13 shows the rx_good_frame signal asserted at the same time as the last valid data on rx_data, this is not always the case. the rx_good_frame and rx_bad_frame signals can in fact be asserted up to 7 clock cycles after the last valid data is presented; for example, this may result from padding at the end of the ethernet frame. this is represented in figure 14 . note that although rx_good_frame is illustrated, the same timing applies to rx_bad_frame. either the rx_good_frame or rx_bad_frame signal will, however, always be asserted before the next frame ? s data begins to appear on rx_data. figure 13: normal frame reception rx_clk rx_data[7:0] rx_data[15:8] rx_data[23:16] rx_data[31:24] rx_data[39:32] rx_data[47:40] rx_data[55:48] rx_data[63:56] rx_data_valid[7:0] rx_good_frame rx_bad_frame ff ff sa sa sa sa l/t l/t d d ff da da da da da da sa sa d d d d d d d d ff 03 00 00 d d d d d d d d d d xip2104
10-gigabit ethernet mac with xgmii or xaui v2.1 18 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r frame reception with errors the case of an unsuccessful frame reception (for example, a runt frame or a frame with an incorrect fcs) can be seen in figure 15 . in this case, the rx_bad_frame signal is asserted to the client at the end of the frame. it is then the responsibility of the client to drop the data already transferred for this frame. figure 14: late arrival of rx_good_frame rx_clk rx_data_valid[7:0] rx_good_frame 7f 00 ff up to 7 clocks xip2105 figure 15: frame reception with error rx_clk rx_data[7:0] rx_data[15:8] rx_data[23:16] rx_data[31:24] rx_data[39:32] rx_data[47:40] rx_data[55:48] rx_data[63:56] rx_data_valid[7:0] rx_good_frame rx_bad_frame ff ff sa sa sa sa l/t l/t d d ff da da da da da da sa sa d d d d d d d d ff 03 00 00 d d d d d d d d d d xip2106
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 19 product specification 1-800-255-7778 r client-supplied fcs passing if the mac core is configured to pass the fcs field to the client (see "configuration registers" on page 22 ), this is handled as shown in figure 16 . in this case, any padding inserted into the frame to meet ethernet minimum frame length specifications will be left intact and passed to the client. note that even though the fcs is passed up to the client, it is also verified by the mac core, and rx_bad_frame is asserted if the fcs check fails. vlan tagged frames the reception of a vlan tagged frame (if enabled) is represented in figure 17 . the vlan frame is passed to the client so that the frame can be identified as vlan tagged; this is followed by the tag control information bytes, v1 and v2. more information on the interpretation of these bytes can be found in ieee 802.3ac-1998. figure 16: frame reception with in-band fcs field rx_clk rx_data[7:0] rx_data[15:8] rx_data[23:16] rx_data[31:24] rx_data[39:32] rx_data[47:40] rx_data[55:48] rx_data[63:56] rx_data_valid[7:0] rx_good_frame rx_bad_frame ff ff sa sa sa sa l/t l/t d d ff da da da da da da sa sa d d d d d d d d ff 3f 00 00 d d d d d fcs fcs fcs fcs d d d d d xip2107
10-gigabit ethernet mac with xgmii or xaui v2.1 20 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r receive statistics vector the statistics for the frame received are contained within the rx_statistics_vector. the vector is driven synchronously by the receiver clock, rx_clk, following frame reception. the bit field definition for the vector is defined in table 11 . all bit fields, with the exception of byte_valid, are valid only when rx_statistics_valid is asserted. this is illustrated in figure 18 . byte_valid is significant on every rx_clk cycle. figure 17: reception of a vlan tagged frame rx_clk rx_data[7:0] rx_data[15:8] rx_data[23:16] rx_data[31:24] rx_data[39:32] rx_data[47:40] rx_data[55:48] rx_data[63:56] rx_data_valid[7:0] rx_good_frame rx_bad_frame ff ff sa sa sa sa 81 00 v1 v2 ff da da da da da da sa sa l/t l/t d d d d d d ff 03 00 00 d d d d d d d d d d xip2108 figure 18: receiver statistics output timing rx_clk rx_statistics_vector[24:0] rx_statistics_valid xip2109
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 21 product specification 1-800-255-7778 r flow control the flow control block is designed to clause 31 of the ieee p802.3 ethernet standard. the mac can be configured to send pause frames and to act on their reception. these two behaviors can be configured asymmetrically; see "configu- ration registers" on page 22 . transmitting a pause control frame the client sends a flow control frame by asserting pause_req while the pause value is on the pause_val bus. these signals are synchronous with respect to tx_clk. the timing of this can be seen in figure 19 . if the mac core is configured to support transmit flow con- trol, this action causes the mac core to transmit a pause control frame on the link, with the pause parameter set to the value on pause_val in the cycle when pause_req was asserted. this will not disrupt any frame transmission in progress but will take priority over any pending frame transmission. receiving a pause control frame when a pause frame is received by the mac core and the mac core is configured to act upon received pause frames, the following checks are made: the frame is checked to see whether it is well formed (is a valid ethernet frame). if not, the frame is dropped if the destination address does not match the mac control multicast address or the configured source address for the mac ( see "configuration registers" on page 22 ), the frame is passed to the client if the length/type field does not match the mac control type code, the frame is passed up to the client if the opcode field contents do not match the pause opcode, the frame is passed up to the client table 11: rx_statistics_vector description rx stats vector bit name description 24 bad opcode the previous frame received was a flow control frame but contained an opcode that is not supported by the mac. 23 flow control frame the previous frame was a flow control frame with a supported opcode. 22 to 19 number of bytes a binary representation of the number of bytes received on the last clock cycle. this can range from 0 to 8. this is valid on every clock cycle, it is not validated by rx_statistics_valid. 18 vlan frame the last received frame contained a vlan tag in the length/type field. 17 out of bounds the previous frame exceeded the maximum length of a frame. this is only valid when jumbo frames are disabled. 16 control frame the last received frame contained the control frame identifier in the length/type field. 15 to 5 frame length count the length in bytes of the previous received frame. the count will stick at 2047 for any jumbo frames larger than this value. 4 multicast frame high if the destination address in the previous frame contained a multicast address. 3 broadcast frame high if the destination address in the previous frame contained a broadcast address. 2 fcs error this is high if the last frame that was received had an incorrect fcs value. 1 bad frame this is high when the last frame contained errors. 0 good frame this is high if the last frame was error free. figure 19: pause request timing tx_clk pause_val[15:0] pause_req xip2110
10-gigabit ethernet mac with xgmii or xaui v2.1 22 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r if the frame passes all of these checks, the pause value parameter in the frame is then used to inhibit transmitter operation for the time defined in the ethernet specification. this inhibit is implemented using the same back pressure scheme shown in figure 9 . since the received pause frame has been acted upon, it is not passed up to the client by marking it as a bad frame. management interface the management interface is a processor-independent interface with standard address, data, and control signals. it can be used as-is, or a wrapper (not supplied) can be applied to interface to common bus architectures. this interface is used for: configuring the mac core accessing statistics information for use by high layers, e.g., snmp accessing an internal miim interface through the optional xaui configuration and status registers accessing the miim interface through the management registers located in the phy attached to the mac core the management interface is accessed differently, depend- ing on the type of transaction; table 12 is a truth table show- ing which access method is required for each transaction type. these access methods are described in the following sections. host_clk frequency the management interface clock, host_clk, is used to derive the miim clock, mdc, and is therefore subject to some frequency restrictions. this host_clk must be: 10 mhz 133 mhz configuring the mac core to derive the mdc signal from this clock is detailed in mii management interface . configuration registers after power up or reset, the client can reconfigure some of the core parameters from their defaults, such as flow control support and wan/lan connections. configuration of the mac core is performed through a reg- ister bank accessed through the management interface. the configuration registers available in the core are detailed in table 13 . as can be seen, the address has some implicit don ? t-care bits; the configuration words appear at all loca- tions in the ranges described. table 12: management interface transaction types transaction host_miim_sel host_addr[9] configuration 0 1 statistics 0 0 miim access 1 x table 13: configuration registers address description 0x200 receiver configuration (word 0). 0x240 receiver configuration (word 1). 0x280 transmitter configuration. 0x2c0 flow control configuration. 0x300 reconciliation sublayer configuration. 0x340 management configuration.
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 23 product specification 1-800-255-7778 r the register contents for the two receiver configuration words is shown in ta ble 1 4 and ta ble 1 5 . the register contents for the transmitter configuration word are described in table 16 . table 14: receiver configuration word 0 bit default value description 31-0 all ? 0s ? pause frame mac address[31:0]. this address is used by the mac to match against the destination address of any incoming flow control frames. it is also used by the flow control block as the source address (sa) for any outbound flow control frames. the address is ordered so the first byte transmitted/received is the lowest positioned byte in the register; for example, a mac address of aa-bb-cc-dd-ee-ff would be stored in address[47:0] as 0xffeeddccbbaa. table 15: receiver configuration word 1 bit default value description 15-0 all ? 0s ? pause frame mac address[47:32]. see description in ta ble 1 4 . 26-16 n/a reserved 27 0 vlan enable. when this bit is set to ? 1, ? vlan tagged frames will be accepted by the receiver. the maximum payload length will increase by 4 bytes. 28 1 receiver enable. if set to ? 1, ? the receiver block will be operational. if set to ? 0, ? the block will ignore activity on the xgmii rx port. 29 0 in-band crc enable. when this bit is ? 1, ? the mac receiver will pass the crc up to the client as described in "client-supplied fcs passing" on page 19 . when it is ? 0, ? the client will not be passed the fcs. in both cases, the fcs will be verified on the frame. 30 0 jumbo frame enable. when this bit is set to ? 1, ? the mac receiver will accept frames of any length. when this bit is ? 0, ? the mac will only accept frames up to the ethernet legal maximum. 31 0 reset. when this bit is set to ? 1, ? the receiver will be reset. the bit will then automatically revert to ? 0. ? note that this reset will also set all of the receiver configuration registers to their default values. table 16: transmitter configuration word bit default value description 24-0 n/a reserved 25 0 interframe gap stretch mode. if this bit is set to ? 1, ? the core will maintain an interframe gap of n cycles. n is set by the value appearing on the ifg_delay port. this value should be set along with the start signal and kept on the port until the data_ack is received from the mac. this bit has no effect when bit 26 (lan/wan mode) is set to ? 1. ? 26 0 lan/wan mode. when this bit is set to ? 1, ? the transmitter will automatically insert extra idles into the inter frame gap (ifg) to reduce the average data rate to that of the oc-192 sonet payload rate (wan mode). when this bit is set to 0, the transmitter will use normal ethernet inter-frame gaps (lan mode). 27 0 vlan enable. when this bit is set to ? 1, ? the transmitter will allow the transmission of vlan tagged frames.
10-gigabit ethernet mac with xgmii or xaui v2.1 24 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r the register contents for the flow control configuration word are described in table 17 . 28 1 transmit enable. when this bit is ? 1, ? the transmitter is operational. when it is ? 0, ? the transmitter is disabled. 29 0 in-band crc enable. when this bit is ? 1, ? the mac transmitter will expect the crc to be passed in by the client as described in "client-supplied fcs passing" on page 9 . when this bit is ? 0, ? the mac transmitter will append padding as required, compute the crc and append it to the frame. 30 0 jumbo frame enable. when this bit is set to ? 1, ? the mac transmitter will send frames of any length. when this bit is ? 0, ? the mac will only send frames up to the ethernet legal maximum. 31 0 reset. when this bit is set to ? 1, ? the transmitter will be reset. the bit will then automatically revert to ? 0. ? note that this reset will also set all of the transmitter configuration registers to their default values. table 17: flow control configuration word bit default value description 28-0 n/a reserved 29 1 flow control enable (tx). when this bit is ? 1, ? asserting the pause_req signal will send a flow control frame out from the transmitter. when this bit is ? 0, ? asserting the pause_req signal has no effect. 30 1 flow control enable (rx). when this bit is ? 1, ? received flow control frames will inhibit the transmitter operation as described in "receiving a pause control frame" on page 21 . when this bit is ? 0, ? received flow control frames will be passed up to the client. 31 0 reset. when this bit is set to ? 1, ? the flow control block will be reset. the bit will then automatically revert to ? 0. ? note that this reset will also set all of the flow control configuration registers to their default values. table 16: transmitter configuration word (continued) bit default value description
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 25 product specification 1-800-255-7778 r the register contents for the reconciliation sublayer status word are described in table 18 . the register contents for the management configuration word are described in table 19 . writing to the configuration registers through the management interface is depicted in figure 20 . when accessing the configuration registers ( i.e., when host_addr[9] = ? 1 ? and host_miim_sel = ? 0 ? ), the upper bit of host_opcode functions as an active low write-enable signal. the lower host_opcode bit is a ? don ? t care. ? reading from the configuration register words is similar, except that the upper host_opcode bit should be ? 1, ? as shown in figure 21 . in this case, the contents of the register appear on host_rd_data and the host_clk edge after the register address is asserted onto host_addr. table 18: reconciliation sublayer status word bits default value description 27-0 n/a reserved 28 n/a local fault. if this bit is ? 1, ? the rs layer is receiving local fault sequence ordered sets. read-only. 29 n/a remote fault. if this bit is ? 1, ? the rs layer is receiving remote fault sequence ordered sets. read-only. 30 n/a txlock. if this bit is ? 1, ? the digital clock management (dcm) block for the transmit-side clocks (gtx_clk, xgmii_tx_clk, tx_clk) is locked. if this bit is ? 0, ? the dcm is not locked. 31 n/a rxlock. if this bit is ? 1, ? the digital clock management (dcm) block for the receive-side clocks (xgmii_rx_clk, rx_clk) is locked. if this bit is ? 0, ? the dcm is not locked. table 19: management configuration word bits default value description 4-0 all ? 0s ? clock divide[4:0]. see "mii management interface" on page 28 5 0 miim enable. when this bit is ? 1, ? the miim interface can be used to access attached phy devices. when this bit is ? 0, ? the miim interface is disabled and the mdio signal remains in a high impedance state. 31-6 n/a reserved.
10-gigabit ethernet mac with xgmii or xaui v2.1 26 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r operational statistics during operation, the mac core collects statistics on the success and failure of various operations, for processing by station management entities (sta) further up the protocol stack. these statistics are accessed by the host through the management interface. a complete list of statistics supported is described in ta bl e 2 0 . each of these statistic registers is 64 bits wide and therefore must be read in a two-cycle transfer. the timing of this process is shown in figure 22 . six clocks after the read transaction is initiated, the least significant word (lsw) of the statistics counter appears on the host_rd_data bus, and a clock cycle later the most significant word (msw) appears. for accurate statistic values, 64 gtx_clk ticks must elapse after the last frame is sent or received through the mac core. figure 20: configuration register write timing host_clk host_addr[8:0] host_addr[9] host_opcode[1] host_miim_sel host_wr_data[31:0] xip2111 figure 21: configuration register read timing host_clk host_addr[8:0] host_addr[9] host_opcode[1] host_miim_sel host_rd_data[31:0] xip2112 table 20: statistics registers address description 0x000 frames received ok 0x001 frame check sequence errors 0x002 broadcast frames received ok 0x003 multicast frames received ok 0x004 64 byte frames received ok 0x005 65-127 byte frames received ok 0x006 128-255 byte frames received ok 0x007 256-511 byte frames received ok 0x008 512-1023 byte frames received ok 0x009 1024-1518 byte frames received ok 0x00a control frames received ok ( i.e., frames with length/type field matching the mac control type code and having the destination address match either the source address in the configuration register or the mac control multicast address). 0x00b length/type out of range 0x00c vlan tagged frames received ok
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 27 product specification 1-800-255-7778 r in general, frames that are declared ? received ok ? are well formed ethernet frames with valid crcs. frames that are declared ? transmitted ok ? were sent out from the mac with no errors introduced by the mac. 0x00d pause frames received ok ( i.e., control frames with an opcode corresponding to a pause request) 0x00e control frames received with unsupported opcode 0x00f oversize frames received ok 0x010 undersized frames received (less than minimum frame size with valid fcs field) 0x011 fragment frames received (less than minimum frame size with invalid fcs field) 0x012 number of bytes received (bytes counted from da to fcs field inclusive) 0x013 number of bytes transmitted (bytes counted from da to fcs field inclusive) 0x020 frames transmitted 0x021 broadcast frames transmitted 0x022 multicast frames transmitted 0x023 underrun errors. note: this will not count underrun frames of length < 64 bytes. 0x024 control frames transmitted ok 0x025 64 byte frames transmitted ok 0x026 65-127 byte frames transmitted ok 0x027 128-255 byte frames transmitted ok 0x028 256-511 byte frames transmitted ok 0x029 512-1023 byte frames transmitted ok 0x02a 1024-1518 byte frames transmitted ok 0x02b vlan tagged frames transmitted ok 0x02c pause frames transmitted ok 0x02d oversize frames transmitted ok table 20: statistics registers (continued) address description
10-gigabit ethernet mac with xgmii or xaui v2.1 28 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r mii management interface the management interface is also used to access the mii management interface of the mac core; this interface is used to access the managed information block (mib) of the phy components attached to the mac core. the mii management interface supplies a clock to the exter- nal devices, mdc. this clock is derived from the host_clk signal, using the value in the clock divide[4:0] configuration register. the frequency of the mii manage- ment clock is given by the following equation: the frequency of mdc given by this equation should not exceed 2.5 mhz in order to comply with the i eee specifica- tion for this interface. to prevent mdc from being out of specification, the clock divide[4:0] value powers up at 00000, and while this value is in the register, it is impossible to enable the mii management interface. for details of the register map of phy layer devices and a fuller description of the operation of the mii management interface itself, see ieee draft specification p802.3ae d4.1. access to the mii management interface through the man- agement interface is depicted in the timing diagram in figure 23 . figure 22: statistic register read timing host_clk host_addr[8:0] host_addr[9] host_req host_miim_sel host_rd_data[31:0] 6 clocks lsw msw xip2113 f mdc f host_clk clock divide[4:0] 2 ---------------------------------------------------- - =
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 29 product specification 1-800-255-7778 r for mii management transactions, the following points apply: host_opcode maps to the op (opcode) field of the mii management frame host_addr maps to the two address fields of the mii management frame; phy_addr is host_add[9:5], and reg_addr is host_add[4:0] host_wr_data[15:0] maps into the data field of the mii management frame when performing a write operation the data field of the mii management frame maps into host_rd_data[15:0] the mac core signals to the host that it is ready for an mii management transaction by asserting host_miim_rdy. a read or write transaction on the mii management is initiated by a pulse on the host_req signal. this pulse is ignored if the mii management interface already has a transaction in progress. the mac core then disasserts the host_miim_rdy signal while the transaction across the mii management interface is in progress. when the transaction across the mii man- agement interface has been completed, the host_miim_rdy signal will be asserted by the mac core; if the transaction is a read, the data will also be available on the host_rd_data[15:0] bus at this time. xgmii interface the optional xgmii interface is a 312mbps ddr interface, as defined in clause 46 of i eee p 802.3ae d4.1. it is imple- mented using the virtex-ii ddr i/o buffer primitives and uses dcm to adjust clock/data alignment. clock management figure 24 shows how the clocks are used and derived within the core when an xgmii interface is used. note that the gtx_clk signal must have an input buffer ibufg either instanced or inferred for correct operation of the core as shown. a dcm is then used to source this clock onto the global clock routing matrix. also note that the host_clk signal does not have a bufg instanced within the core; this clock buffer must be instanced or inferred by the core user. figure 23: miim access through management interface host_clk host_addr[9:0] host_opcode[1:0] host_req host_miim_sel host_rd_data[15:0] host_wr_data[15:0] host_rdy * * * if a read transaction is initiated, the host_rd_data bus is valid at the point indicated. if a write transaction is initiated, the host_wr_data bus must be valid at the indicated point. simultaneous read and write is not permitted. xip2114
10-gigabit ethernet mac with xgmii or xaui v2.1 30 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r the xgmii_rx_clk is received through an ibufg. this clock is then routed onto a global clock network by connecting it through a dcm to a bufg: this global clock is used by all mac receiver logic. the mac client can obtain this clock by connecting to the rx_clk signal output from the core. pin location considerations the mac core allows for a flexible pinout of the xgmii and the exact pin locations are left to the designer. in doing so, codes of practice and device restrictions must be followed. every virtex-ii and virtex-ii pro device has 8 separate io banks. each io bank has output drive source voltage pads (vcco) that must be connected to the same external voltage reference. for xgmii, this must be 1.5 volts. this will force all io pads within the bank to operate at this volt- age level. io standards, including hstl, which use input differential amplifiers, require voltage reference inputs (vref). these are automatically configured by the place and route tool onto predefined pins (see the virtex-ii user guide or vir- tex-ii pro user guide for all devices and packages). approx- imately one of every 12 io pins within an io bank will be configured as a vref pin. for xgmii which uses hstl_i, all vref pins must be connected externally to 0.75 volts. ios should be grouped in their own separate clock domains. xgmii contains two of these: xgmii_rxd[31:0] and xgmii_rxc[3:0], which are centered with respect to xgmii_rx_clk; xgmii_txd[31:0] and xgmii_txc[3:0], which are centered with respect to xgmii_tx_clk. it is recommended that these be separated into separate io banks. unused ios in these banks, if tied to ground, will help to reduce jitter by providing a low impedance path for ground currents. xaui interface the optional xaui interface is a 4-lane, 3.125gbps-per-lane current mode logic interface, as defined in clauses 47 and 48 of ieee p802.3ae d4.1. a diagram of the xaui block is shown in figure 25 . the main components of the xaui block are: the transmitter component the receiver component the management register component the rocketio multi gigabit transceivers (mgts) the management registers of the xaui block have an miim interface which is accessed through the core host interface as if it were an externally connected phy. the rocketio mgts provide some of the xaui functionality, such as 8b10b encoding/decoding and the pma serdes. the synchronization and idle pattern generation logic are generated as clb logic. figure 24: clock management in core with xgmii interface dcm clkin clk0 clk90 fb dcm clkin clk0 fb bufg bufg ibufg ibufg bufg tx_clk rx_clk gtx_clk fddrrse xgmii_tx_clk xgmii_rx_clk mac core xip2115
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 31 product specification 1-800-255-7778 r clock management figure 26 shows how the clocks are used and derived within the core when an xaui interface is used. note that the ref_clk signal must have an input buffer either instanced or inferred for correct operation of the core. this refclk signal must be a high purity clock as speci- fied for rocketio reference clocks in the virtex-ii pro user guide. also note that the host_clk signal does not have a bufg instanced within the core; this clock buffer must be instanced or inferred by the core user. in this configuration, the tx_clk and rx_clk signals are actually the same net; the elastic buffer in the mgt is used to cross into a common clock domain. if only the xaui con- figuration is to be used in the final application, some optimi- zations to client logic can be made. figure 25: functional diagram of the xaui block transmit engine receive engine management to mac lane 0 lane 1 lane 2 lane 3 mdio interface mgt mgt mgt mgt xip2116
10-gigabit ethernet mac with xgmii or xaui v2.1 32 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r pin location considerations the four mgts of the xaui block are channel bonded as described in the virtex-ii pro user?s guide . the lane 0 mgt is the channel bond master, lanes 1 and 2 are 1-hop slaves, and lane 3 is a 2-hop slave. it is therefore recommended that if the xaui interface is to be split across the top and bottom of the fpga, lanes 0 and 1 are placed on one edge and lanes 2 and 3 on the opposite edge, with lane 0 and lane 2 aligned vertically with each other. this will allow the optimum routing for the time-critical channel bonding signals. xaui register block the xaui core contains registers as defined in clause 45 of the ieee p802.3ae d4.1 draft. if the xaui_type_sel pin is ? 1, ? the register set is that of a dte xgxs entity. if the xaui_type_sel pin is ? 0, ? the register set is that of a 10gbase-x pcs/pma entity. note that this pin is regis- tered into the core at power-up and hard reset, and cannot be changed after that time; it is intended to be a static flag. these registers are accessed through the miim interface of the mac. the xaui_prtad port designates the address of the xaui/pcs on the miim interface. dte xgxs registers the management registers for the dte xgxs implementa- tion of the xaui block are shown in table 21 ; the dte xgxs occupies device address 5. figure 26: clock management in core using xaui interface txusrclk refclk txusrclk2 rxusrclk rxusrclk2 gt_xaui_2 txusrclk refclk txusrclk2 rxusrclk rxusrclk2 gt_xaui_2 txusrclk refclk txusrclk2 rxusrclk rxusrclk2 gt_xaui_2 dcm clkin clk0 fb bufg bufg ibufg tx_clk rx_clk refclk txusrclk refclk txusrclk2 rxusrclk rxusrclk2 gt_xaui_2 mac core xip2117 table 21: dte xgxs registers register address register name 5.0 dte xs control 1 5.1 dte xs status 1 5.2,3 device identifier 5.4 dte xs speed ability 5.5,6 devices in package 5.7 reserved 5.8 dte xs status 2 5.9 to 5.13 reserved 5.14,15 package identifier 5.16 to 5.23 reserved 5.24 10g dte xgxs lane status 5.25 10g dte xgxs test control 5.26 to 5.65 535 reserved
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 33 product specification 1-800-255-7778 r the dte xs control register is described in table 22 . the dte xs status register is described in table 23 . table 22: dte xs control register 1 (register 5.0) bit(s) name description attributes default value 5.0.15 reset 1 = block reset 0 = normal operation the xaui block is reset when this bit is set to ? 1. ? it returns to ? 0 ? when the reset is complete. r/w self-clearing 0 5.0.14 loopback 1 = enable loopback mode 0 = disable loopback mode the xaui block will loop the signal in the mgts back into the receiver. r/w 0 5.0.13 speed selection the block always returns ? 1 ? for this bit and ignores writes. r/o 1 5.0.12 reserved the block always returns ? 0 ? for this bit and ignores writes. r/o 0 5.0.11 power down 1 = power down mode 0 = normal operation when set to ? 1, ? the mgts are placed in a low power state. this bit requires a reset (see bit 5.0.15) to clear. r/w 0 5.0.10:7 reserved the block always returns ? 0s ? for these bits and ignores writes. r/o 0 5.0.6 speed selection the block always return ? 1 ? for this bit and ignores writes. r/o 1 5.0.5:2 speed selection the block always returns ? 0s ? for these bits and ignores writes. r/o all ? 0s ? 5.0.1:0 reserved the block always returns ? 0s ? for these bits and ignores writes. r/o all ? 0s ? table 23: dte xs status register 1 (register 5.1) bit(s) name description attributes default value 5.1.15:8 reserved the block always returns ? 0s ? for these bits and ignores writes. r/o all ? 0s ? 5.1.7 local fault 1 = local fault detected 0 = no local fault detected this bit is set to ? 1 ? whenever either of the bits 5.8.11, 5.8.10 are set to ? 1. ? r/o - 5.1.6:3 reserved the block always returns ? 0s ? for these bits and ignores writes. r/o all ? 0s ?
10-gigabit ethernet mac with xgmii or xaui v2.1 34 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r the dte xs identifier register is described in ta bl e 2 4 . the dte xs speed ability register is described in table 25 . the devices in package register is described in table 26 . 5.1.2 dte xs receive link status 1 = the dte xs receive link is up 0 = the dte xs receive link is down this is a latching low version of bit 5.24.12. r/o self-setting - 5.1.1 power down ability the block always returns ? 1 ? for this bit. r/o 1 5.1.0 reserved the block always returns ? 0 ? for this bit and ignores writes. r/o 0 table 23: dte xs status register 1 (register 5.1) (continued) bit(s) name description attributes default value table 24: dte xs identifier (registers 5.2 and 5.3) bit(s) name description attributes default value 5.2.15:0 dte xs identifier the block always returns ? 0 ? for these bits and ignores writes r/o all ? 0s ? 5.3.15:0 dte xs identifier the block always returns ? 0 ? for these bits and ignores writes r/o all ? 0s ? table 25: dte xs speed ability register (register 5.4) bit(s) name description attribute default value 5.4.15:1 reserved the block always returns ? 0 ? for these bits and ignores writes r/o all ? 0s ? 5.4.0 10g capable the block always returns ? 1 ? for this bit and ignores writes. r/o 1 table 26: devices in package (register 5.5 and 5.6) bit(s) name description attributes default value 5.6.15 vendor- specific device present the block always returns ? 0 ? for this bit. r/o 0 5.6.14:0 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 5.6.15:6 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 5.5.5 dte xs present the block always returns ? 1 ? for this bit. r/o all ? 0s ? 5.5.4 phy xs present the block always returns ? 0 ? for this bit. r/o 0 5.5.3 pcs present the block always returns ? 0 ? for this bit. r/o 0 5.5.2 wis present the block always returns ? 0 ? for this bit. r/o 0 5.5.1 pma/pmd present the block always returns ? 0 ? for this bit. r/o 0 5.5.0 clause 22 device present the block always returns ? 0 ? for this bit. r/o 0
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 35 product specification 1-800-255-7778 r the dte xs status register 2 is described in ta bl e 2 7 . the package identifier register is described in ta bl e 2 8 the dte lane status register is described in table 29 table 27: dte xs status register 2 (register 5.8) bit(s) name description attributes default value 5.8.15:14 device present the block shall always return ? 10. ? r/o ? 10 ? 5.8.13:12 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 5.8.11 transmit local fault 1 = fault condition on transmit path 0 = no fault condition on transmit path r/o latching high - 5.8.10 receive local fault 1 = fault condition on receive path 0 = no fault condition on receive path r/o latching high - 5.8.9:0 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? table 28: package identifier (registers 5.14 and 5.15) bit(s) name description attributes default value 5.14.15:0 package identifier the block always returns ? 0 ? for these bits. r/o all ? 0s ? 5.15.15:0 package identifier the block always returns ? 0 ? for these bits. r/o all ? 0s ? table 29: dte xs lane status register (register 5.24) bit(s) name description attributes default value 5.24.15:13 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 5.24.12 dte xgxs lane alignment status 1 = dte xgxs receive lanes aligned; 0 = dte xgxs receive lanes not aligned. ro - 5.24.11 pattern testing ability the block always returns ? 1 ? for this bit. r/o 1 5.24.10:4 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 5.24.3 lane 3 sync 1 = lane 3 is synchronized; 0 = lane 3 is not synchronized. r/o - 5.24.2 lane 2 sync 1 = lane 2 is synchronized; 0 = lane 2 is not synchronized. r/o - 5.24.1 lane 1 sync 1 = lane 1 is synchronized; 0 = lane 1 is not synchronized. r/o - 5.24.0 lane 0 sync 1 = lane 0 is synchronized; 0 = lane 0 is not synchronized. r/o -
10-gigabit ethernet mac with xgmii or xaui v2.1 36 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r the dte xs test control register is shown in ta b l e 3 0 . 10gbase-x pcs/pma registers the management registers for the 10g base-x pcs/pma implementation of the xaui block are shown in table 31 . the 10gbase-x pcs/pma occupies device addresses 1 and 3. the pma/pmd control register 1 is described in ta b l e 3 2 . table 30: 10g dte xs test control register (register 5.25) bit(s) name description attributes default value 5.25.15:3 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 5.25.2 transmit test pattern enable 1 = transmit test pattern enable 0 = transmit test pattern disabled r/w 0 5.25.1:0 test pattern select 11 = reserved 10 = mixed frequency test pattern 01 = low frequency test pattern 00 = high frequency test pattern r/w ? 00 ? table 31: 10gbase-x pcs/pma registers register address register name 1.0 pma/pmd control 1 1.1 pma/pmd status 1 1.2,3 device identifier 1.4 pma/pmd speed ability 1.5,6 devices in package 1.7 10g pma/pmd control 2 1.8 10g pma/pmd status 2 1.9 reserved 1.10 10g pmd receive signal ok 1.11 to 1.13 reserved 1.14,15 package identifier 1.16 to 1.65 535 reserved 3.0 pcs control 1 3.1 pcs status 1 3.2,3 device identifier 3.4 pcs speed ability 3.5,6 devices in package 3.7 10g pcs control 2 3.8 10g pcs status 2 3.9 to 3.13 reserved 3.14,15 package identifier 3.16 to 3.23 reserved 3.24 10gbase-x pcs status 3.25 10gbase-x pcs test control 3.26 to 3.65 535 reserved
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 37 product specification 1-800-255-7778 r the pma/pmd status register 1 is described in ta bl e 3 3 . table 32: pma/pmd control register 1 (register 1.0) bit(s) name description attributes default value 1.0.15 reset 1 = block reset 0 = normal operation the xaui block is reset when this bit is set to ? 1. ? it returns to ? 0 ? when the reset is complete. r/w self-clearing 0 1.0.14 reserved the block always returns ? 0 ? for this bit and ignores writes. r/o 0 1.0.13 speed selection the block always returns ? 1 ? for this bit and ignores writes. r/o 1 1.0.12 reserved the block always returns ? 0 ? for this bit and ignores writes. r/o 0 1.0.11 power down 1 = power down mode 0 = normal operation when set to ? 1, ? the mgts are placed in a low power state. this bit requires a reset (see bit 1.0.15) to clear. r/w 0 1.0.10:7 reserved the block always returns ? 0 ? for these bits and ignores writes. r/o all ? 0s ? 1.0.6 speed selection the block always return ? 1 ? for this bit and ignores writes. r/o 1 1.0.5:2 speed selection the block always returns ? 0s ? for these bits and ignores writes. r/o all ? 0s ? 1.0.1 reserved the block always returns ? 0 ? for this bit and ignores writes r/o all ? 0s ? 1.0.0 loopback 1 = enable loopback mode 0 = disable loopback mode the xaui block will loop the signal in the mgts back into the receiver. r/w 0 table 33: pma/pmd status register 1 (register 1.1) bit(s) name description attributes default value 1.1.15:8 reserved the block always returns ? 0 ? for this bit. r/o 0 1.1.7 local fault 1 = local fault detected 0 = no local fault detected this bit is set to ? 1 ? whenever either of the bits 1.8.11, 1.8.10 are set to ? 1. ? r/o - 1.1.6:3 reserved the block always returns ? 0 ? for this bit. r/o 0 1.1.2 receive link status the block always returns ? 1 ? for this bit. r/o 1 1.1.1 power down ability the block always returns ? 1 ? for this bit. r/o 1 1.1.0 reserved the block always returns ? 0 ? for this bit. r/o 0
10-gigabit ethernet mac with xgmii or xaui v2.1 38 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r the device identifier register is described in ta b l e 3 4 . the pma/pms speed ability register is shown in ta b l e 3 5 . the devices in package register is described in table 36 table 34: device identifier (registers 1.2 and 1.3) bit(s) name description attributes default value 1.2.15:0 dte xs identifier the block always returns ? 0 ? for these bits and ignores writes. r/o all ? 0s ? 1.3.15:0 dte xs identifier the block always returns ? 0 ? for these bits and ignores writes. r/o all ? 0s ? table 35: pma/pmd speed ability register (register 14) bit(s) name description attribute default value 1.4.15:1 reserved the block always returns ? 0 ? for these bits and ignores writes. r/o all ? 0s ? 1.4.0 10g capable the block always returns ? 1 ? for this bit and ignores writes. r/o 1 table 36: devices in package (register 1.5 and 1.6) bit(s) name description attributes default value 1.6.15 vendor- specific device present the block always returns ? 0 ? for this bit. r/o 0 1.6.14:0 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 1.6.15:6 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 1.5.5 dte xs present the block always returns ? 0 ? for this bit. r/o 0 1.5.4 phy xs present the block always returns ? 0 ? for this bit. r/o 0 1.5.3 pcs present the block always returns ? 1 ? for this bit. r/o 1 1.5.2 wis present the block always returns ? 0 ? for this bit. r/o 0 1.5.1 pma/pmd present the block always returns ? 1 ? for this bit. r/o 1 1.5.0 clause 22 device present the block always returns ? 0 ? for this bit. r/o 0
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 39 product specification 1-800-255-7778 r the 10g pma/pmd control register 2 is described in table 37 . the 10g pma/pmd status register 2 is described in table 38 table 37: 10g pma/pmd control register 2 (register 1.7) bit(s) name description attributes default value 1.7.15:3 reserved the block always returns ? 0 ? for these bits and ignores writes r/o all ? 0s ? 1.7.2:0 pma/pmd type selection the block always returns ? 100 ? for these bits and ignores writes. this corresponds to the 10gbase-x pma/pmd. r/o ? 100 ? table 38: 10g pma/pmd status register 2 (register 1.8) bit(s) name description attributes default value 1.8.15:14 device present the block always returns ? 10 ? for these bits. r/o ? 10 ? 1.8.13 transmit local fault ability the block always returns ? 0 ? for this bit. r/o 0 1.8.12 receive local fault ability the block always returns ? 0 ? for this bit. r/o 0 1.8.9 reserved the block always returns ? 0 ? for this bit. r/o 0 1.8.8 pmd transmit disable ability the block always returns ? 0 ? for this bit. r/o 0 1.8.7 10gbase-sr ability the block always returns ? 0 ? for this bit. r/o 0 1.8.6 10gbase-lr ability the block always returns ? 0 ? for this bit. r/o 0 1.8.5 10gbase-er ability the block always returns ? 0 ? for this bit. r/o 0 1.8.4 10gbase-lx4 ability the block always returns ? 1 ? for this bit. r/o 1 1.8.3 10gbase-sw ability the block always returns ? 0 ? for this bit. r/o 0 1.8.2 10gbase-lw ability the block always returns ? 0 ? for this bit. r/o 0 1.8.1 10gbase-ew ability the block always returns ? 0 ? for this bit. r/o 0 1.8.0 pma loopback ability the block always returns ? 1 ? for this bit. r/o 1
10-gigabit ethernet mac with xgmii or xaui v2.1 40 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r the 10g pmd signal receive ok register is described in ta bl e 3 9 . the package identifier register is described in ta bl e 4 0 . the pcs control register 1 is described in table 41 . table 39: 10g pmd signal receive ok register (register 1.10) bit(s) name description attributes default value 1.10.15:5 reserved the block always returns ? 0s ? for these bits. r/o all ? 0s ? 1.10.4 pmd receive signal ok 3 1 = signal ok on receive lane 3 0 = signal not ok on receive lane 3 this is the value of the signal_detect[3] port. r/o - 1.10.3 pmd receive signal ok 2 1 = signal ok on receive lane 2 0 = signal not ok on receive lane 2 this is the value of the signal_detect[2] port. r/o - 1.10.2 pmd receive signal ok 1 1 = signal ok on receive lane 1 0 = signal not ok on receive lane 1 this is the value of the signal_detect[1] port. r/o - 1.10.1 pmd receive signal ok 0 1 = signal ok on receive lane 0 0 = signal not ok on receive lane 0 this is the value of the signal_detect[0] port. r/o - 1.10.0 global pmd receive signal ok 1 = signal ok on all receive lanes 0 = signal not ok on all receive lanes r/o - table 40: package identifier (registers 1.14 and 1.15) bit(s) name description attributes default value 1.14.15:0 package identifier the block always returns ? 0 ? for these bits. r/o all ? 0s ? 1.15.15:0 package identifier the block always returns ? 0 ? for these bits. r/o all ? 0s ? table 41: pcs control register 1 (register 3.0) bit(s) name description attributes default value 3.0.15 reset 1 = block reset 0 = normal operation the xaui block is reset when this bit is set to ? 1. ? it returns to ? 0 ? when the reset is complete. r/w self-clearing 0 3.0.14 10gbase-r loopback the block always returns ? 0 ? for this bit and ignores writes. r/o 0 3.0.13 speed selection the block always returns ? 1 ? for this bit and ignores writes. r/o 1 3.0.12 reserved the block always returns ? 0 ? for this bit and ignores writes. r/o 0
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 41 product specification 1-800-255-7778 r the pcs status register 1 is described in table 42 . the device identifier register is described in ta b l e 4 3 . 3.0.11 power down 1 = power down mode 0 = normal operation when set to ? 1, ? the mgts are placed in a low power state. this bit requires a reset (see bit 3.0.15) to clear. r/w 0 3.0.10:7 reserved the block always returns ? 0 ? for these bits and ignores writes. r/o all ? 0s ? 3.0.6 speed selection the block always return ? 1 ? for this bit and ignores writes. r/o 1 3.0.5:2 speed selection the block always returns ? 0s ? for these bits and ignores writes. r/o all ? 0s ? 3.0.1:0 reserved the block always returns ? 0 ? for this bit and ignores writes r/o all ? 0s ? table 41: pcs control register 1 (register 3.0) (continued) bit(s) name description attributes default value table 42: pcs status register 1 (register 3.1) bit(s) name description attributes default value 3.1.15:8 reserved the block always returns ? 0 ? s for these bits and ignores writes r/o all ? 0s ? 3.1.7 local fault 1 = local fault detected 0 = no local fault detected this bit is set to ? 1 ? whenever either of the bits 3.8.11, 3.8.10 are set to ? 1. ? r/o - 3.1.6:3 reserved the block always returns ? 0s ? for these bits and ignores writes r/o all ? 0s ? 3.1.2 pcs receive link status 1 = the pcs receive link is up 0 = the pcs receive link is down this is a latching low version of bit 3.24.12 r/o self-setting - 3.1.1 power down ability the block always returns ? 1 ? for this bit. r/o 1 3.1.0 reserved the block always returns ? 0 ? for this bit and ignores writes r/o 0 table 43: device identifier (registers 3.2 and 3.3) bit(s) name description attributes default value 3.2.15:0 pcs identifier the block always returns ? 0 ? for these bits and ignores writes r/o all ? 0s ? 3.3.15:0 pcs identifier the block always returns ? 0 ? for these bits and ignores writes r/o all ? 0s ?
10-gigabit ethernet mac with xgmii or xaui v2.1 42 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r the pcs speed ability register is described in table 44 . the devices in package register is described in table 45 . the 10g pcs control register 2 is described in ta ble 4 6 . the 10g pcs status register 2 is described in ta b l e 4 7 . table 44: pcs speed ability register (register 3.4) bit(s) name description attribute default value 3.4.15:1 reserved the block always returns ? 0 ? for these bits and ignores writes. r/o all ? 0s ? 3.4.0 10g capable the block always returns ? 1 ? for this bit and ignores writes. r/o 1 table 45: devices in package (register 3.5 and 3.6) bit(s) name description attributes default value 3.6.15 vendor specific device present the block always returns ? 0 ? for this bit. r/o 0 3.6.14:0 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 3.6.15:6 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 3.5.5 dte xs present the block always returns ? 0 ? for this bit. r/o 0 3.5.4 phy xs present the block always returns ? 0 ? for this bit. r/o 0 3.5.3 pcs present the block always returns ? 1 ? for this bit. r/o 1 3.5.2 wis present the block always returns ? 0 ? for this bit. r/o 0 3.5.1 pma/pmd present the block always returns ? 1 ? for this bit. r/o 1 3.5.0 clause 22 device present the block always returns ? 0 ? for this bit. r/o 0 table 46: 10g pcs control register 2 (register 3.7) bit(s) name description attributes default value 3.7.15:2 reserved the block always returns ? 0 ? for these bits and ignores writes. r/o all ? 0s ? 3.7.1:0 pcs type selection the block always returns ? 01 ? for these bits and ignores writes. r/o ? 01 ? table 47: 10g pcs status register 2 (register 3.8) bit(s) name description attributes default value 3.8.15:14 device present the block always returns ? 10. ? r/o ? 10 ? 3.8.13:12 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 3.8.11 transmit local fault 1 = fault condition on transmit path 0 = no fault condition on transmit path r/o latching high -
10-gigabit ethernet mac with xgmii or xaui v2.1 ds201 (v2.1) june 24, 2002 www.xilinx.com 43 product specification 1-800-255-7778 r the package identifier register is described in ta ble 4 8 . the 10gbase-x status register is described in table 49 . 3.8.10 receive local fault 1 = fault condition on receive path 0 = no fault condition on receive path r/o latching high - 3.8.9:3 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 3.8.2 10gbase-w capable the block always returns ? 0 ? for this bit. r/o 0 3.8.1 10gbase-x capable the block always returns ? 1 ? for this bit. r/o 1 3.8.0 10gbase-r capable the block always returns ? 0 ? for this bit. r/o 0 table 47: 10g pcs status register 2 (register 3.8) (continued) bit(s) name description attributes default value table 48: package identifier (registers 3.14 and 3.15) bit(s) name description attributes default value 3.14.15:0 package identifier the block always returns ? 0 ? for these bits. r/o all ? 0s ? 3.15.15:0 package identifier the block always returns ? 0 ? for these bits. r/o all ? 0s ? table 49: 10gbase-x status register (register 3.24) bit(s) name description attributes default value 3.24.15:13 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 3.24.12 10gbase-x lane alignment status 1 = 10gbase-x receive l anes aligned; 0 = 10gbase-x receive l anes not aligned. ro - 3.24.11 pattern testing ability the block always returns ? 1 ? for this bit. r/o 1 3.24.10:4 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 3.24.3 lane 3 sync 1 = lane 3 is synchronized; 0 = lane 3 is not synchronized. r/o - 3.24.2 lane 2 sync 1 = lane 2 is synchronized; 0 = lane 2 is not synchronized r/o - 3.24.1 lane 1 sync 1 = lane 1 is synchronized; 0 = lane 1 is not synchronized. r/o - 3.24.0 lane 0 sync 1 = lane 0 is synchronized; 0 = lane 0 is not synchronized. r/o -
10-gigabit ethernet mac with xgmii or xaui v2.1 44 www.xilinx.com ds201 (v2.1) june 24, 2002 1-800-255-7778 product specification r the 10gbase-x test control register is described in ta bl e 5 0 . mdio interface the mdio interface pins (mdc, mdio_in, mdio_out, mdio_tri) are brought out of the core separately for maxi- mum flexibility. they can be: connected to an iobuf to drive an external tristate bus connected through individual ibufs and obufs to a level shifter to create a fully compliant clause 45 mdio interface connected to an internal soc management interface references ieee p 802.3ae d4.1 draft specification ieee 802.3-2000 virtex-ii user guide virtex-ii pro user guide optional blocks xilinx can deliver instances of the core with the optional functional blocks left out. this can significantly reduce logic consumption in lightweight applications. the optional blocks are: statistical counters included or excluded from the netlist xgmii or xaui interface to the phy table 51 provides some indication of the resource savings that can be made. note that these numbers are approxi- mate and will depend to some extent on the customer design. please contact xilinx for more information on these configu- rations. related information xilinx products are not intended for use in life support appli- ances, devices, or systems. use of a xilinx product in such applications without the written consent of the appropriate xilinx officer is prohibited. copyright 1991-2002 xilinx, inc. all rights reserved. ordering information this xilinx logicore product is provided under the signonceip site license . a free evaluation version of the product is available from the xilinx ip evaluation lounge , at http://www.xilinx.com/ipcenter/ipevaluation/index.htm . please refer to the product page for this core on the xilinx ip center , http://www.xilinx.com/ipcenter/index.htm , for part number and pricing information. to purchase this core, con- tact your local xilinx sales representative . information on additional xilinx logicore modules is available on the xil- inx ip center. table 50: 10gbase-x test control register (register 5.25) bit(s) name description attributes default value 3.25.15:3 reserved the block always returns ? 0 ? for these bits. r/o all ? 0s ? 3.25.2 transmit test pattern enable 1 = transmit test pattern enable 0 = transmit test pattern disabled r/w 0 3.25.1:0 test pattern select 11 = reserved 10 = mixed frequency test pattern 01 = low frequency test pattern 00 = high frequency test pattern r/w ? 00 ? table 51: optional blocks - approximate resource usage optional block xgmii xaui statistics included 3750 slices 4400 slices statistics excluded 3000 slices 3700 slices

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